DTMES 2022 - Presentation
Wendemagegnehu Tsegaye Beyene, Meta, USA
Abstract - The presentation starts with an introduction to memory systems in computing devices such as computers, tablets or smartphones. Then, an in-depth analysis of standard memory systems for low-power and high-performance applications is provided. The interactions between the signaling, clocking architecture and packaging technology of a memory interface as well as how these interactions determine the achievable data rates and power efficiency are discussed. Signaling and clocking schemes for standard memories, including the latest varies main and mobile memories are detailed and compared against each other. The emerging 2.5D/3D and future memory systems are also presented. To analyze and compare different state-of-the-art memory interfaces, the following metrics are used in the analysis: cost, power efficiency, bandwidth, design complexity, signal and power integrity, thermal solution, and form factor. The talk will provide an in-depth understanding of high-speed memory interfaces; learn about the interactions between the signaling, clocking architecture and packaging technology of a memory interface, and find out how those interactions determine the achievable data rates and power efficiency. The presentation will conclude by demonstrating how this knowledge can be used to analyze and compare different state-of-the-art memory interfaces to help attendees implement or select a solution which best fits their specific application..
Wedemagegnehu Tsegaye was born in Addis Ababa, Ethiopia. He received the B.S. and M.S. degrees in electrical engineering
from Columbia University, New York, NY, USA, in 1988 and 1991, respectively, and the Ph.D. degree in electrical and computer engineering
from the University of Illinois at Urbana-Champaign, USA, in 1997. In the past, he was employed by IBM, Hewlett-Packard, and Agilent
Technologies. In 2000, he joined Rambus Inc., Los Altos, CA, USA, and served as a senior principal engineer responsible for signal integrity of
multi-gigabit parallel and serial interfaces. During 2017-2020 he served as principal engineer and manager responsible for signal and power integrity
analysis of high-performance FPGA including fabric and high-speed I/O subsystems as well as I/O modeling. In 2020 he joined Facebook as an Analog &
Mixed-Signal Architect in Facebook Reality Lab. Dr. Beyene has authored or co-authored numerous refereed publications in various leading IEEE Transactions and conferences.
These publications covered various disciplines including package and interconnect modeling, analysis and optimization. He is currently an Associate Editor of IEEE Trans.
On CPMT and is a Senior Member of Institute of Electrical and Electronic Engineers (IEEE). He also serves on several leading technical program committees, including EPEPS and SPI. He is an
Elected Associate Fellow of Ethiopian Academy of Sciences and is also recently elected as a Distinguished Lecturer of the IEEE EMCS for 2021-2022 and IEEE EPS Society for 2020-2024.