DTMES 2022 - Presentation

Sub picosecond resolution time to digital converter implementation using routing resources on FPGA
Roza Teklehaimanot Siecha,AAiT, Ethiopia

Abstract - A time to digital converter, converts the time interval between two clock events into a digital form. Among the different parameters of TDC, this paper mainly focuses on achieving a sub picosecond time resolution TDC on FPGA. TDCs can be implemented on ASIC or on FPGA. FPGA based TDC design have the advantage over ASIC based designs because of its flexibility of implementation, short design time, possibility of reprogramming and simplicity for prototyping. The problem with FPGA based TDC design is the delay elements that are mostly used for TDC implementation are the carry chains available in the FPGA. The carry chains are basic elements with the smallest delay and good linearity. This puts limitation on the highest achievable resolution. Using the carry chain delay elements, the best time resolution achieved so far for TDC on FPGA is 10ps. The motivation for this study is to find a way to achieve a higher time resolution TDC design on FPGA. Routing resources are abundant in the FPGA architecture. It covers almost 90% of the FPGA area. Using the routing resources in the FPGA it is possible to achieve a high time resolution TDC. This paper presents a sub picosecond TDC implementation on FPGA using routing resources as delay elements and the different factors that affect the resolution and linearity of the TDC. It also studies the available routing resources (wires, switchboxes and the programmable interconnect points (PIPs)) in FPGA and presents findings on how to configure the FPGA routing manually to achieve an optimal time resolution as well as linearity for TDC. With this approach it was possible to achieve a high resolution TDC in the range of 2ps and 4ps.

Roza Teklehaimanot Siecha was born in 1989 in Ethiopia. She obtained her Bachelor's Degree in Electrical and computer Engineering from Bahir Dar University, Bahir Dar, Ethiopia and her Master's degree in Embedded electronics from polytechnic university of Turin, Turin, Italy. Roza is currently a PhD candidate at both Addis Ababa University, Ethiopia and Ku Leuven University, Belgium and working in radiation hardened digital design of PLLs on FPGA. Her research interest is in Embedded Electronics and FPGA based digital designs, in general.