DTMES 2022 - Presentation

Abstract - The semiconductor industry has always been plagued by design re-spins often times attributable to the complexity of the designs that need to be taped out. As we move into the sub-10nm process nodes, as the interposer (package) technologies begin to support sub-2um line geometries, as the designs become more analog in nature where parasitic effects become very critical, the room available for design errors will only decrease, thereby increasing the probability for design mistakes. Part of the reason for design re-spins in the past has been that simulation based design optimization techniques have had limited success due to the long design cycle times, often requiring designers to take short cuts. Can Machine Learning (ML) help alleviate this problem? In this presentation I will focus on optimization, prediction, and uncertainty quantification with a focus on both the fundamental and advanced concepts. These techniques will be applied to real world examples arising in 3DIC, Integrated Voltage Regulators (IVR), Wireless Power Transfer (WPT), sub-THz mmwave, and Serdes channels to illustrate the advantages of developing ML based techniques related to Signal, Power and Thermal Integrity. Fundamentals associated with surrogate modeling, Gaussian process, Bayesian methods, neural networks, sensitivity analysis, etc will be discussed during the course of this tutorial..

Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) (http://www.prc.gatech.edu). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML: https://publish.illinois.edu/advancedelectronics/) and Leads the Heterogeneous Integration area, at the SRC JUMP ASCENT Center (https://ascent.nd.edu/). Prior to joining GT, he was with IBM working on packaging for supercomputers. He is the author of 530+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies (JMD and E-System Design), and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.